1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and is applied, for example, to a high-breakdown-voltage transistor which is disposed in a row decoder.
2. Description of the Related Art
In recent years, the integration density and capacity of nonvolatile memories, such as NAND flash EEPROMs, have been increased, and the chip size has been reduced. In order to reduce the chip size, it is necessary to reduce the unit cell size and the size of peripheral circuit parts. If attention is paid to the peripheral circuit, the gate length and device area of each transistor are reduced, thereby promoting chip shrink.
However, as is known, if the gate length and device region width of the transistor are decreased, the threshold value lowers and becomes non-uniform due to a reverse narrow channel effect, leading to deterioration in transistor characteristics (e.g. Jpn. Pat. Appln. KOKAI Publication No. 2001-319978). It is thus necessary to provide a structure of the transistor, which can suppress the occurrence of these problems and can prevent degradation of transistor characteristics.
The reverse narrow channel effect occurs at an interface between a channel region, which is a device region, and a device isolation insulating film, where a corner portion of the device region is present. At this corner portion, an active region is recessed and a gate electrode extends to the active region, and as a result, an electric field from the gate electrode concentrates. Consequently, turn-on occurs more easily in this part than the other part (central part) of the channel region, and the threshold lowers. In addition, with the development of microfabrication, as the channel width becomes narrower, the characteristics of the corner portion where turn-on occurs become more dominant. Thus, with the decrease in channel width, the threshold of turn-on of the transistor lowers.
Besides, it is considered that the reverse narrow channel effect is greatly influenced by removal of impurities (e.g. boron (B)) from the channel region.
In addition, in the case where a device isolation insulating film is formed of, e.g. polysilazane (PSZ: Partial Stabilized Zircon), there is a tendency that charge in the device isolation insulating film accumulates in the substrate at the above-described corner portion, and degrades the transistor characteristics.
It is necessary, therefore, to perform profile tuning of a diffusion layer, which is designed specifically for a peripheral transistor, and to improve the transistor characteristics, thereby to prevent degradation in transistor characteristics.
However, since the peripheral transistor is formed at the same time as the memory cell, it is difficult to consistently and integrally perform the processes for the memory cell and peripheral transistor.
Consequently, the number of additional processes, such as ion implantation that is performed specifically for the peripheral transistor, increases, and the manufacturing cost rises.